• Fan-in (FIWLP)

    (Bumping, Repassivation, RDL)
  • eWLCSP

    (encapsulated WLCSP)
  • Fan-out (FOWLP)
  • eWLB

    (embedded wafer level BGA)
  • 2.5D and 3D SiP eWLB

  • Integrated Passive Devices
  • IPD

  • Through Silicon Via
  • TSV for CIS

  • TSV for 3D IC


Compact, high performance packages for rapidly shrinking product form factors

Proven leadership in innovative FOWLP solutions with over 1.7 Billion units shipped

Innovative 2D/2.5D/3D FOWLP packages with size, performance and cost advantages

Enhanced performance and size reduction with silicon IPDs

3D TSV capabilities covering mid-end-of-line through backend assembly and test

  • Laminate FC SiP
  • Laminate FC + WB SiP
  • SiP Modules
  • Leadframe WB SiP
  • Laminate Stack Die WB SiP


.Electronic system or sub-system integrates multiple active and passive components for higher performance, functionality, processing speeds and low cost

.Leading SiP technology portfolio incorporates all the key technical building blocks

Advanced design rules for 2.5D and 3D FOWLP or SiP configurations

High density SMT with high accuracy component placement

Advanced mold tech for complex topography SiP applications

Highly automated process modules

Tight process control to ensure consistency and high yield

.One stop turnkey solution - wafer to fully tested SiP modules

  • fcCuBE
  • fcFBGA
  • fcBGA
  • Bare die fcPoP
  • (flip chip package-on-package)

  • Molded Laser fcPoP
  • (flip chip package-on-package)

  • flip chip on Leadframe
  • (FCOL)

  • fcMIS
  • (flip chip on Molded interconnect System)


Patented fcCuBE : proven low cost, high performance advanced flip chip technology

Fine pitch Cu pillar and Bond-on-Lead (BOL) interconnection for higher routing density at a lower cost Scalability to finer bump pitches, higher I/O and advanced fab nodes at a lower cost

High speed fcBGA-H offering for network/communication market fcPoP and hybrid flip chip + wirebond configurations for increased functional integration in a smaller form factor, and Pre-stacking of memory on logic for PoP packages

Leadership in low cost substrate technologies – Embedded Trace Substrate (ETS), Molded Interconnect System (MIS) and Single Layer laminate substrate

Wire Bond Package

  • PBGA
  • FBGA
  • (Side by Side,Stached Die)

  • Package-on-Package
  • MEMS
  • Memory Card
  • LGA


Advanced wirebond technology in a cost competitive manufacturing location

Comprehensive range of single die, multi die, thermally enhanced and stacked die packages

Thin outline LGA suitable for high performance and/or portable applications

Low profile PoP provides flexibility in mixing and matching IC technologies in a thin package

Innovative process capabilities to enable MEMS and sensors chipset integration and fusion

Cost effective package approach for memory card formats

Laminate / Lead Frame

  • Discrete Packages:TO,SOD,FBP
  • Flip Chip on Leadframe(FCOL)
  • DIP
  • SOP
  • SOT
  • DFN
  • QFP
  • QFN-mr
  • QFN-dr
  • QFN


Extensive experience in leadframe and discrete packages for a wide range of applications

Patented FCOL on MIS lead frame offers leading-edge QFN package for proven better

electrical and thermal performance, particularly in power management applications

MIS advantages

Ultra small, thin technology achieves product miniaturization

Superior RF, electrical, thermal and reliability performance

Fine line routing for high density I/O

Supports a wide range of wirebond, flip chip, SiP and PoP package configurations

Proven substrate technology with over 1B units shipped since 2010

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